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Nov 2006
HYB18M512160BF-6 HYE18M512160BF-6 HYB18M512160BF-7.5 HYE18M512160BF-7.5
DRAMs for Mobile Applications 512-Mbit DDR Mobile-RAM RoHS compliant
Internet Data Sheet
Rev.1.80
HY[B/E]18M512160BF 512-Mbit DDR Mobile-RAM
HYB18M512160BF-6; HYE18M512160BF-6 HYE18M512160BF-7.5 Revision History: Previous Version: all 18 Rev.1.80 1.70 2006-11
converted into QAG template table 15: added typ. values
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com Internet Data Sheet 2 Rev.1.80, 2006-11 07092007-3E44-UTNM
HY[B/E]18M512160BF 512-Mbit DDR Mobile-RAM
Overview
1
1.1
* * * * * * * * * * * * * * * *
Overview
Features
4 banks x 8 Mbit x 16 organization Double-data-rate architecture : two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted / received with data; to be used in capturing data at the receiver DQS is edge-aligned with data for READs and center-aligned with data for WRITEs Differential clock input (CK / CK) Commands entered on positive CK edge; data and mask data are referenced to both edges of DQS Four internal banks for concurrent operation Programmable CAS latency: 2 and 3 Programmable burst length: 2, 4, 8 and 16 Programmable drive strength (full, half, quarter) Auto refresh and self refresh modes 8192 refresh cycles / 64ms Auto precharge Commercial (0C to +70C) and Extended (-25oC to +85oC) operating temperature range 60-ball Very Thin FBGA package (10.5 x 10.5 x 1.0 mm) RoHS Compliant Product1)
Power Saving Features * * * * * * Low supply voltages: VDD = 1.70 V - 1.90 V, VDDQ = 1.70 V - 1.90 V Optimized operating (IDD0 , IDD4), self refresh (IDD6) and standby currents (IDD2 , IDD3) DDR I/O scheme with no DLL Programmable Partial Array Self Refresh (PASR) Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor Clock Stop, Power-Down and Deep Power-Down modes Performance -6 CL = 3 CL = 2 Access Time (tACmax) 166 83 5.5 - 7.5 133 66 6.5 Unit MHz MHz ns
Table 1
Part Number Speed Code Clock Frequency (fCKmax)
Table 2 Item Banks Rows Columns
Memory Addressing Scheme Addresses BA0, BA1 A0 - A12 A0 - A9
1)RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. Internet Data Sheet 3 Rev.1.80, 2006-11 07092007-3E44-UTNM
HY[B/E]18M512160BF 512-Mbit DDR Mobile-RAM
Overview
Table 3 Type
1)
Ordering Information Package P-VFBGA-60-1 P-VFBGA-60-1 P-VFBGA-60-1 P-VFBGA-60-1 Description 166 MHz 4 Banks x 8 Mbit x 16 Low Power DDR SDRAM 133 MHz 4 Banks x 8 Mbit x 16 Low Power DDR SDRAM 166 MHz 4 Banks x 8 Mbit x 16 Low Power DDR SDRAM 133 MHz 4 Banks x 8 Mbit x 16 Low Power DDR SDRAM
Commercial Temperature Range HYB18M512160BF-6 HYB18M512160BF-7.5 HYE18M512160BF-6 HYE18M512160BF-7.5
Extended Temperature Range
1) HYB / HYE: Designator for memory products (HYB: standard temp. range; HYE: extended temp. range) 18M: 1.8V DDR Mobile-RAM 512: 512 MBit density 160: 16 bit interface width B: die revision F: green product -6/-7.5: speed grades (min. clock cycle time)
1.2
Pin Configuration
Figure 1
Standard Ballout 512-Mbit DDR Mobile-RAM (Top View)
Internet Data Sheet
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Rev.1.80, 2006-11 07092007-3E44-UTNM
HY[B/E]18M512160BF 512-Mbit DDR Mobile-RAM
Overview
1.3
Description
The HY[B/E]18M512160BF is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. The HY[B/E]18M512160BF uses a double-data-rate architecture to achieve high-speed operation. The doubledata-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE access for the DDR Mobile-RAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, onehalf clock cycle data transfers at the I/O pins. The HY[B/E]18M512160BF is especially designed for mobile applications. It operates from a 1.8V power supply. Power consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor (OCTS); it can further be reduced by using the programmable Partial Array Self Refresh (PASR). A conventional data-retaining Power-Down (PD) mode is available as well as a non-data-retaining Deep PowerDown (DPD) mode. For further power-savings the clock may be stopped during idle periods. The HY[B/E]18M512160BF is housed in a 60-ball very thin FBGA package. It is available in Commercial (0C to 70C) and Extended (-25oC to +85oC) temperature range.
Figure 2
Functional Block Diagram 5 Rev.1.80, 2006-11 07092007-3E44-UTNM
Internet Data Sheet
HY[B/E]18M512160BF 512-Mbit DDR Mobile-RAM
Overview
1.4
Table 4 Ball CK, CK CKE
Pin Definition and Description
Pin Description Type Input Input Detailed Function Clock: CK and CK are differential clock inputs. All address and control inputs are sampled on crossing of the positive edge of CK and negative edge of CK. Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides precharge powerdown and self refresh operation (all banks idle), or active power-down (row active in any bank). CKE must be maintained HIGH throughout read and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE are disabled during self refresh. Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. Data Inputs/Output: Bi-directional data bus (16 bit) Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered with write data. Used to capture write data. LDQS corresponds to the data on DQ0 - DQ7; UDQS to the data on DQ8 - DQ15. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. DM may be driven HIGH, LOW, or floating during READs. LDM corresponds to the data on DQ0 - DQ7; UDM to the data on DQ8 - DQ15. Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVATE, READ, WRITE or PRECHARGE command is being applied. BA0, BA1 also determine which mode register is to be loaded during a MODE REGISTER SET command (MRS or EMRS). Address Inputs: Provide the row address for ACTIVE commands and the column address and Auto Precharge bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 (=AP) is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10=LOW) or all banks (A10=HIGH). If only one bank is to be precharged, the bank is selected by BA0 and BA1. The address inputs also provide the op-code during a MODE REGISTER SET command.
CS
Input
RAS, CAS, WE DQ0 - DQ15
Input I/O
LDQS, UDQS I/O
LDM, UDM
Input
BA0, BA1
Input
A0 - A12
Input
VDDQ VSSQ VDD VSS
N.C.
Supply I/O Power Supply: Isolated power for DQ output buffers for improved noise immunity: VDDQ = 1.70 V - 1.90 V Supply I/O Ground Supply Power Supply: Power for the core logic and input buffers, VDD = 1.70 V - 1.90 V Supply Ground - No Connect
Internet Data Sheet
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Rev.1.80, 2006-11 07092007-3E44-UTNM
HY[B/E]18M512160BF 512-Mbit DDR Mobile-RAM
Functional Description
2
Functional Description
The 512-Mbit DDR Mobile-RAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM. READ and WRITE accesses to the DDR Mobile-RAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the banks, A0 - A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the DDR Mobile-RAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command description and device operation.
2.1 2.1.1
Register Definition Mode Register
The Mode Register is used to define the specific mode of operation of the DDR Mobile-RAM. This definition includes the selection of a burst length (bits A0-A2), a burst type (bit A3) and a CAS latency (bits A4-A6). The Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements results in unspecified operation. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. MR Mode Register Definition
BA1 0 BA0 0 A12 0 A11 0 A10 0 A9 0
(BA[1:0] = 00B)
A8 0 A7 0 A6 A5 CL A4 A3 BT A2 A1 BL A0
Field CL
Bits [6:4]
Type w
Description CAS Latency 010 2 011 3 Note: All other bit combinations are RESERVED. Burst Type 0 Sequential 1 Interleaved Burst Length 001 2 010 4 011 8 100 16 Note: All other bit combinations are RESERVED.
BT
3
w
BL
[2:0]
w
Internet Data Sheet
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Rev.1.80, 2006-11 07092007-3E44-UTNM
HY[B/E]18M512160BF 512-Mbit DDR Mobile-RAM
Functional Description
2.2
Table 5 CKEn-1 L
Function Truth Tables
Truth Table - CKE CKEn L Current State Power-Down Self Refresh Deep Power-Down L H Power-Down Self Refresh Deep Power-Down H L All Banks Idle Bank(s) Active All Banks Idle All Banks Idle H H Command X X X DESELECT or NOP DESELECT or NOP X DESELECT or NOP DESELECT or NOP AUTO REFRESH BURST TERMINATE Action Maintain Power-Down Maintain Self Refresh Maintain Deep Power-Down Exit Power-Down Exit Self Refresh Exit Deep Power-Down Enter Precharge Power-Down Enter Active Power-Down Enter Self Refresh Enter Deep Power-Down Notes
1)2)3)4) 1) to 4) 1) to 4) 1) to 5) 1) to 5) 1) to 4), 6) 1) to 4) 1) to 4) 1) to 4) 1) to 4) 1) to 4)
see Table 6 and Table 7
1) 2) 3) 4) 5) 6)
CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. Current state is the state immediately prior to clock edge n. COMMAND n is the command registered at clock edge n; ACTION n is a result of COMMAND n. All states and sequences not shown are illegal or reserved. DESELECT or NOP commands should be issued on any clock edges occurring during tXP or tXSR period. Exit from DEEP POWER DOWN requires the same command sequence as for power-up initialization.
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HY[B/E]18M512160BF 512-Mbit DDR Mobile-RAM
Functional Description
Table 6 Any Idle
Current State Bank n - Command to Bank n CS H L L L L RAS CAS WE Command / Action X H L L L H H L H H L H H H L X H H L L L L H L L H H L L H X H H H L H L L H L L L H L L DESELECT (NOP / continue previous operation) NO OPERATION (NOP / continue previous operation) ACTIVE (select and activate row) AUTO REFRESH MODE REGISTER SET READ (select column and start Read burst) WRITE (select column and start Write burst) PRECHARGE (Deactivate row in bank or banks) READ (truncate Read and start new Read burst) WRITE (truncate Read and start new Write burst) PRECHARGE (truncate Read and start Precharge) BURST TERMINATE READ (truncate Write and start Read burst) WRITE (truncate Write and start Write burst) PRECHARGE (truncate Write burst, start Precharge) Notes
1)2)3)4)5)6) 1) to 6) 1) to 6) 1) to 7) 1) to 7) 1) to 6), 8) 1) to 6), 8) 1) to 6), 9) 1) to 6), 8) 1) to 6), 8), 10) 1) to 6), 9) 1) to 6), 11) 1) to 6), 8), 12) 1) to 6), 8) 1) to 6), 9),12)
Current State
Row Active
L L L
Read (AutoPrecharge Disabled) Write (AutoPrecharge
L L L L L L L
1) This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 5) and after tXP or tXSR has been met (if the previous state was power-down or self refresh). 2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3) Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts / accesses and no register accesses are in progress. Read: A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 4) The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and according to Table 7. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank is in the "idle" state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank is in the "row active" state. Read with AP Enabled: Starts with registration of a READ command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. Write with AP Enabled: Starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. 5) The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the DDR Mobile-RAM is in the "all banks idle" state. Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met. Once tMRD is met, the DDR Mobile-RAM is in the "all banks idle" state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks are in the idle state.
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Rev.1.80, 2006-11 07092007-3E44-UTNM
HY[B/E]18M512160BF 512-Mbit DDR Mobile-RAM
Functional Description
6) All states and sequences not shown are illegal or reserved. 7) Not bank-specific; requires that all banks are idle and no bursts are in progress. 8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 9) May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 10) A WRITE command may be applied after the completion of the Read burst; otherwise, a BURST TERMINATE command must be used to end the Read burst prior to issuing a WRITE command. 11) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank. 12) Requires appropriate DM masking.
Table 7 Any Idle
Current State Bank n - Command to Bank m (different bank) CS H L X L L L L L L L L L L L L L L L L L L L L RAS CAS WE Command / Action X H X L H H L L H H L L H H L L H H L L H H L X H X H L L H H L L H H L L H H L L H H L L H X H X H H L L H H L L H H L L H H L L H H L L DESELECT (NOP / continue previous operation) NO OPERATION (NOP / continue previous operation) Any command otherwise allowed to bank m ACTIVE (select and activate row) READ (select column and start Read burst) WRITE (select column and start Write burst) PRECHARGE (Deactivate row in bank or banks) ACTIVE (select and activate row) READ (truncate Read and start new Read burst) WRITE (truncate Read and start Write burst) PRECHARGE (Deactivate row in bank or banks) ACTIVE (select and activate row) READ (truncate Write and start Read burst) WRITE (truncate Write and start new Write burst) PRECHARGE (Deactivate row in bank or banks) ACTIVE (select and activate row) READ (truncate Read and start new Read burst) WRITE (truncate Read and start Write burst) PRECHARGE (deactivate row in bank or banks) ACTIVE (select and activate row) READ (truncate Write and start Read burst) WRITE (truncate Write and start new Write burst) Notes
1)2)3)4)5)6) 1) to 6) 1) to 6) 1) to 6) 1) to 7) 1) to 7) 1) to 6) 1) to 6) 1) to 7) 1) to 8) 1) to 6) 1) to 6) 1) to 7), 9) 1) to 7) 1) to 6) 1) to 6) 1) to 7) 1) to 8) 1) to 6) 1) to 6) 1) to 7) 1) to 7)
Current State
Row Activating, Active, or Precharging
Read (AutoPrecharge Disabled) Write (AutoPrecharge Disabled) Read (with AutoPrecharge) Write (with AutoPrecharge)
1) to 6) PRECHARGE (Deactivate row in bank or banks) 1) This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 5) and after tXP or tXSR has been met (if the
previous state was power-down or self refresh). 2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.
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Rev.1.80, 2006-11 07092007-3E44-UTNM
HY[B/E]18M512160BF 512-Mbit DDR Mobile-RAM
Functional Description
3) Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts / accesses and no register accesses are in progress. Read: A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Read with AP Enabled: see following text. Write with AP Enabled: see following text. 3a. The Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states can each be broken into two parts: the access period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, ACTIVE, PRECHARGE, READ and WRITE commands to the other bank may be applied; during the access period, only ACTIVE and PRECHARGE commands to the other bank may be applied. In either case, all other related limitations apply (e.g. contention between READ data and WRITE data must be avoided). 4) AUTO REFRESH, SELF REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle. 5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6) All states and sequences not shown are illegal or reserved. 7) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 8) A WRITE command may be applied after the completion of the Read burst; otherwise, a BURST TERMINATE command must be used to end the Read burst prior to issuing a WRITE command. 9) Requires appropriate DM masking.
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Rev.1.80, 2006-11 07092007-3E44-UTNM
HY[B/E]18M512160BF 512-Mbit DDR Mobile-RAM
Electrical Characteristics
3
3.1
Table 8 Parameter
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings Symbol min. Values max. 2.7 2.7 V V V V C C C W mA -0.3 -0.3 -0.3 -0.3 0 -25 -55 - - Unit
Power Supply Voltage Power Supply Voltage for Output Buffer Input Voltage Output Voltage Operation Case Temperature Storage Temperature Power Dissipation Short Circuit Output Current Commercial Extended
VDD VDDQ VIN VOUT TC TC TSTG PD IOUT
VDDQ + 0.3 VDDQ + 0.3
+70 +85 +150 0.7 50
Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Table 9 Parameter Input capacitance: CK, CK Delta input capacitance: CK, CK Input capacitance: all other input-only pins Delta input capacitance: all other input-only pins Input/output capacitance: DQ, DQS, DM Delta input/output capacitance: DQ, DQS, DM Pin Capacitances1)2)3) Symbol min. Values max. 2.5 0.25 2.5 0.5 4.5 0.5 pF pF pF pF pF pF 1.5 - 1.5 - 3.5 - Unit
CI1 CDI1 CI2 CDI2 CIO CDIO
1) These values are not subject to production test but verified by device characterization. 2) Input capacitance is measured according to JEP147 procedure for measuring capacitance using a vector network analyzer. VDD, VDDQ are applied and all other pins (except the pin under test) are floating. DQ's should be in high impedance state. This may be achieved by pulling CKE to low level. 3) Although DM is an input-only pin, it's input capacitance models the input capacitance of the DQ and DQS pins.
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Rev.1.80, 2006-11 07092007-3E44-UTNM
HY[B/E]18M512160BF 512-Mbit DDR Mobile-RAM
Electrical Characteristics
Table 10 Parameter
Electrical Characteristics1)2) Symbol min. Values max. 1.90 1.90 1.0 1.5 V V A A V V V V V V V V V V V V - - - - - - -
3) 3) 4)
Unit Notes
Power Supply Voltage Power Supply Voltage for DQ Output Buffer Input leakage current Output leakage current Input high voltage Input low voltage Clock Inputs (CK, CK) DC input voltage DC input differential voltage AC input differential voltage AC differential cross point voltage DC input high voltage DC input low voltage AC input high voltage AC input low voltage Data Outputs (DQ0 - DQ15, LDQS, UDQS) Output high voltage
VDD VDDQ IIL IOL VIH VIL VIN VID(DC) VID(AC) VIX VIHD(DC) VILD(DC) VIHD(AC) VILD(AC) VOH VOL
1.70 1.70 -1.0 -1.5 0.8 x VDDQ -0.3 -0.3 0.4 x VDDQ 0.6 x VDDQ 0.4 x VDDQ 0.7 x VDDQ -0.3 0.8 x VDDQ -0.3 0.9 x VDDQ -
Address and Command Inputs (BA0, BA1, A0 - A12, CKE, CS, RAS, CAS, WE)
VDDQ + 0.3 0.2 x VDDQ
VDDQ + 0.3
VDDQ + 0.6 VDDQ + 0.6 0.6 x VDDQ VDDQ + 0.3
0.3 x VDDQ
Data Inputs (DQ0 - DQ15, LDM, UDM, LDQS, UDQS) - - - - - -
VDDQ + 0.3 0.2 x VDDQ
- 0.1 x VDDQ
Output low voltage 1) 0 C TC 70 C (comm.); -25 C TC 85 C (ext.); All voltages referenced to VSS. VSS and VSSQ must be at same potential.
2) See Table 13 and Figure 3 for overshoot and undershoot definition. 3) VID is the magnitude of the difference between the input level on CK and the input level on CK. 4) The value of VIX is expected to be equal to 0.5 x VDDQ and must track variations in the DC level.
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Rev.1.80, 2006-11 07092007-3E44-UTNM
HY[B/E]18M512160BF 512-Mbit DDR Mobile-RAM
Electrical Characteristics
3.2
Table 11 Parameter
AC Characteristics
AC Characteristics1)2)3)4) Symbol tAC tDQSCK tCH tCL tHP tCK tDS tDH tDIPW tIS tIH tIPW tLZ tHZ tDQSQ tQH tQHS tDQSS tDQSH tDQSL tDSS tDSH tMRD tWPRES tWPST tWPRE tRPRE tRPST tRAS tRC tRFC tRCD tRP tRRD tWR - 7.5 min. max. min. max. 2 5.5 2.0 6.5 2 5.5 2.0 6.5 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 min(tCL,tCH) min(tCL,tCH) 6 - 7.5 - 12 - 15 - 0.6 - 0.75 - TBD - 0.85 - 0.6 - 0.75 - TBD - 0.85 - 2.1 - 1.7 - 1.1 - 1.3 - 1.3 - 1.5 - 1.1 - 1.3 - 1.3 - 1.5 - 2.7 - 3.0 - 1.0 - 1.0 - - 5.5 - 6.5 - 0.5 - 0.6 tHP-tQHS - tHP-tQHS - - 0.65 - 0.75 0.75 1.25 0.75 1.25 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.2 - 0.2 - 0.2 - 0.2 - 2 - 2 - 0 - 0 - 0.4 0.6 0.4 0.6 0.25 - 0.25 - 0.9 1.1 0.9 1.1 - - 0.7 1.1 0.4 0.6 0.4 0.6 42 70,000 45 70,000 60 - 65 - 72 - 75 - 18 18 12 15 - - - - 22.5 22.5 15 15 - - - - -6 Unit Notes ns 5)6) ns 5)6) tCK - tCK - ns 7)8) ns 9) ns ns ns ns ns ns ns ns ns ns ns tCK tCK tCK tCK tCK tCK ns tCK tCK tCK
10)11)12) 10)11)13) 10)11)12) 10)11)13) 14) 12)15)16) 13)15)16) 12)15)16) 13)15)16) 14) 17) 17) 18) 8) 8)
DQ output access time from CK/CK DQS output access time from CK/CK Clock high-level width Clock low-level width Clock half period Clock cycle time DQ and DM input setup time DQ and DM input hold time DQ and DM input pulse width Address and control input setup time Address and control input hold time
CL = 3 CL = 2 fast slew rate slow slew rate fast slew rate slow slew rate fast slew rate slow slew rate fast slew rate slow slew rate
Address and control input pulse width DQ & DQS low-impedance time from CK/CK DQ & DQS high-impedance time from CK/CK DQS - DQ skew DQ / DQS output hold time from DQS Data hold skew factor Write command to 1st DQS latching transition DQS input high-level width DQS input low-level width DQS falling edge to CK setup time DQS falling edge hold time from CK MODE REGISTER SET command period Write preamble setup time Write postamble Write preamble Read preamble CL = 3 CL = 2 Read postamble ACTIVE to PRECHARGE command period ACTIVE to ACTIVE command period AUTO REFRESH to ACTIVE/AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period ACTIVE bank A to ACTIVE bank B delay WRITE recovery time
- - - - - -
19) 20)
-
21)
tCK - ns 22) ns 22) ns 22) ns ns ns ns
22) 22) 22) 22)
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HY[B/E]18M512160BF 512-Mbit DDR Mobile-RAM
Electrical Characteristics Table 11 Parameter Auto precharge write recovery + precharge time AC Characteristics1)2)3)4) (cont'd) Symbol tDAL -6 min. max. (tWR/tCK) + (tRP/tCK) 1 - 120 - tCK+tIS - 2 - - 64 - 7.8 - 7.5 Unit Notes min. max. tCK 23)
Internal write to Read command delay tWTR 1 - tCK - Self refresh exit to next valid command delay tXSR 120 - ns 22) Exit power down delay tXP tCK+tIS - ns CKE minimum high or low time tCKE 2 - tCK - Refresh period tREF - 64 ms - Average periodic refresh interval (8192 rows) tREFI - 7.8 s 24) 1) 0 C TC 70 C (comm.); -25 C TC 85 C (ext.); VDD = VDDQ = 1.70 V - 1.90 V. All voltages referenced to VSS.
2) All parameters assume proper device initialization. 3) The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for signals other than CK/CK is VDDQ/2. 4) All AC timing characteristics assume an input slew rate of 1.0 V/ns. 5) The output timing reference level is VDDQ/2. 6) Parameters tac and tDQSCK are specified for full drive strength and a reference load as shown below. This circuit is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. For half drive strength with a nominal load of 10pF parameters tAC and tDQSCK are expected to be in the same range. However, these parameters are not subject to production test but are estimated by device characterization. Use of IBIS or other simulation tools for system validation is suggested.
7) Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 8) tQH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCL, tCH). tQHS accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 9) The only time that the clock frequency is allowed to change is during power-down, self-refresh or clock stop modes. 10) DQ, DM and DQS input slew rate is measured between VILD(DC) and VIHD(AC) (rising) or VIHD(DC) and VILD(AC) (falling). 11) DQ, DM and DQS input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic. 12) Input slew rate 1.0 V/ns.. 13) Input slew rate 0.5V/ns and < 1.0 V/ns. 14) These parameters guarantee device timing. They are verified by device characterization but are not subject to production test. 15) The transition time for address and command inputs is measured between VIH and VIL. 16) A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter. 17) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 18) tDQSQ consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 19) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 20) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly.
Internet Data Sheet
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Rev.1.80, 2006-11 07092007-3E44-UTNM
HY[B/E]18M512160BF 512-Mbit DDR Mobile-RAM
Electrical Characteristics
21) A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-down element in the system. It is recommended to turn off the weak pull-down element during read and write bursts (DQS drivers enabled). 22) These parameters account for the number of clock cycles and depend on the operating frequency, as follows: no. of clock cycles = specified delay / clock period ; round to the next higher integer. 23) tDAL = (tWR / tCK) + (tRP / tCK): for each of the terms above, if not already an integer, round to the next higher integer. 24) A maximum of eight AUTOREFRESH commands can be posted to the DDR Mobile-RAM device, meaning that the maximum absolute interval between any Refresh command and the next Refresh command is 8 * tREFI.
Table 12 Parameter
Output Slew Rate Characteristics 1) Typical Range TBD TBD Minimum 0.7 0.3 0.7 Maximum 2.5 1.0 1.4 Unit V/ns V/ns Notes
2)
Pullup and Pulldown Slew Rate (Full Drive Buffer) Pullup and Pulldown Slew Rate (Half Drive Buffer) Output Slew Rate Matching Ratio (Pullup to Pulldown)
2)
3)
1) Output slew rate is measured between VILD(DC) and VIHD(AC) (rising) or VIHD(DC) and VILD(AC) (falling). 2) The parameter is measured using a 20pF capacitive load connected to VSSQ. 3) The ratio of the pullup slew rate to the pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
Table 13 Parameter
AC Overshoot / Undershoot Specification Maximum 0.9 0.9 3.0 3.0 Unit V V V-ns V-ns Notes - - - -
Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot Maximum overshoot area above VDD Maximum undershoot area below VSS
Figure 3
AC Overshoot and Undershoot Definition
Internet Data Sheet
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Rev.1.80, 2006-11 07092007-3E44-UTNM
HY[B/E]18M512160BF 512-Mbit DDR Mobile-RAM
Electrical Characteristics
3.3
Table 14
Operating Currents
Maximum Operating Currents1)2)3)4)5) Symbol Values -6 - 7.5 50 mA 70 Unit
Parameter & Test Conditions Operating one bank active-precharge current:
tRC = tRCmin; tCK = tCKmin; CKE is HIGH; CS is HIGH between valid commands; address inputs are SWITCHING; data bus inputs are STABLE
IDD0 IDD2P IDD2PS IDD2N IDD2NS IDD3P IDD3PS IDD3N IDD3NS IDD4R IDD4W IDD5 IDD6
Precharge power-down standby current:
all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE
0.70
0.70
mA
Precharge power-down standby current with clock stop:
all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE
0.60
0.60
mA
Precharge non power-down standby current:
all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE
18
15
mA
Precharge non power-down standby current with clock stop:
all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE
1.5
1.5
mA
Active power-down standby current:
one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE
2
2
mA
Active power-down standby current with clock stop:
one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE
1.5
1.5
mA
Active non power-down standby current:
one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE
25
22
mA
Active non power-down standby current with clock stop:
one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE
2.5
2.5
mA
Operating burst read current:
one bank active; BL = 4; CL = 3; tCK = tCKmin; continuous read bursts; IOUT = 0 mA; address inputs are SWITCHING; 50% data change each burst transfer
105
75
mA
Operating burst write current:
one bank active; BL = 4; tCK = tCKmin; continuous write bursts; address inputs are SWITCHING; 50% data change each burst transfer
110
75
mA
Auto-Refresh current:
tRC = tRFCmin; tCK = tCKmin; burst refresh; CKE is HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE
185
135
mA
Self refresh current:
CKE is LOW; CK = LOW, CK = HIGH; address and control inputs are STABLE; data bus inputs are STABLE
see Table 15
A
IDD8 Deep Power Down current 1) 0 C TC 70 C (comm.); -25 C TC 85 C (ext.); VDD = VDDQ = 1.70 V - 1.90 V.
256)
A
Recommended Operating Conditions unless otherwise noted 2) IDD specifications are tested after the device is properly intialized and measured at 133 MHz for -7.5 and 166 MHz for -6 speed grade.
Internet Data Sheet
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Rev.1.80, 2006-11 07092007-3E44-UTNM
HY[B/E]18M512160BF 512-Mbit DDR Mobile-RAM
Electrical Characteristics
3) Input slew rate is 1.0 V/ns. 4) Definitions for IDD: LOW is defined as VIN 0.1 * VDDQ ; HIGH is defined as VIN 0.9 * VDDQ ; STABLE is defined as inputs stable at a HIGH or LOW level; SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles; - data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE 5) All parameters are measured with no output loads. 6) IDD8 current is typical.
Table 15
Self Refresh Currents Max. Temperature 85 C 70 C 45 C 25 C 85 C 70 C 45 C 25 C 85 C 70 C 45 C 25 C Symbol typ. Values max. 900 - - - 780 - - - 670 - - - A 710 510 320 280 540 370 240 210 420 290 210 170 Units Notes
1)2)3)
Parameter & Test Conditions Self Refresh Current: Self refresh mode, full array activation (PASR = 000) Self Refresh Current: Self refresh mode, half array activation (PASR = 001) Self Refresh Current: Self refresh mode, quarter array activation (PASR = 010)
IDD6
-
1) 0 C TC 70 C (comm.); -25 C TC 85 C (ext.); VDD = VDDQ = 1.70 V - 1.90 V. 2) The On-Chip Temperature Sensor (OCTS) adjusts the refresh rate in self refresh mode to the component's actual temperature with a much finer resolution than supported by the 4 imperature levels as defined by JEDEC for TCSR. At production test the sensor is calibrated, and IDD6 max. current is measured at 85C. Typ. values are obtained from device characterization. 3) For commercial temperature range part (HYB), the max. value indicated for 85C applies to 70C.
Internet Data Sheet
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Rev.1.80, 2006-11 07092007-3E44-UTNM
HY[B/E]18M512160BF 512-Mbit DDR Mobile-RAM
Electrical Characteristics
3.4
Table 16
Pullup and Pulldown Characteristics
Full Drive Strength and Half Drive Strength1) Full Drive Strength Half Drive Strength PD Current (mA) min. 0.00 1.27 2.55 3.82 5.09 6.36 7.64 8.91 10.16 10.80 10.80 10.80 10.80 10.80 10.80 10.80 10.80 10.80 10.80 10.80 max. 0.00 8.42 12.30 14.95 16.84 18.20 19.30 20.30 21.20 21.60 22.00 22.45 22.73 23.21 23.67 24.14 24.61 25.08 25.54 26.01 26.48 26.95 PU Current (mA) min. 0.00 -1.27 -2.55 -3.82 -5.09 -6.36 -7.64 -8.91 -10.16 -10.80 -10.80 -10.80 -10.80 -10.80 -10.80 -10.80 -10.80 -10.80 -10.80 -10.80 max. 0.00 -8.42 -12.30 -14.95 -16.84 -18.20 -19.30 -20.30 -21.20 -21.60 -22.00 -22.45 -22.73 -23.21 -23.67 -24.14 -24.61 -25.08 -25.54 -26.01 -26.48 -26.95 max. 0.00 -18.53 -26.80 -32.80 -37.05 -40.00 -42.50 -44.57 -46.50 -47.48 -48.50 -49.40 -50.05 -51.35 -52.65 -53.95 -55.25 -56.55 -57.85 -59.15 -60.45 -61.75
Voltage (V) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.85 0.90 0.95 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 1.90
PD Current (mA) min. 0.00 2.80 5.60 8.40 11.20 14.00 16.80 19.60 22.40 23.80 23.80 23.80 23.80 23.80 23.80 23.80 23.80 23.80 23.80 23.80 max. 0.00 18.53 26.80 32.80 37.05 40.00 42.50 44.57 46.50 47.48 48.50 49.40 50.05 51.35 52.65 53.95 55.25 56.55 57.85 59.15 60.45 61.75
PU Current (mA) min. 0.00 -2.80 -5.60 -8.40 -11.20 -14.00 -16.80 -19.60 -22.40 -23.80 -23.80 -23.80 -23.80 -23.80 -23.80 -23.80 -23.80 -23.80 -23.80 -23.80
1) Above characteristics are specified under best and worst process variation / condition. Temperature (Tcase): Minimum = 0 C / -25C, Maximum = 70C / 85C VDDQ: Minimum = 1.70 V, Maximum = 1.90 V
Full Drive Strength IV Curves 75.0 50.0 25.0 0.0 -25.0 -50.0 -75.0 0.0 0.5 1.0 1.5
PD Min PD Max PU Min PU Max
Half Drive Strength IV Curves 30.0 20.0 10.0 0.0 -10.0 -20.0 -30.0 0.0 0.5 1.0 1.5
PD Min PD Max PU Min PU Max
Figure 4
Full Drive Strength and Half Drive Strength 19 Rev.1.80, 2006-11 07092007-3E44-UTNM
Internet Data Sheet
HY[B/E]18M512160BF 512-Mbit DDR Mobile-RAM
Package Outlines
4
Package Outlines
Figure 5
P-VFBGA-60-1 (Plastic Very Thin Fine Ball Grid Array Package)
You can find all of our packages, sorts of packing and others in our Qimonda Internet Page "Products": http://www.qimonda.com/products. SMD = Surface Mounted Device Internet Data Sheet 20 Dimensions in mm Rev.1.80, 2006-11 07092007-3E44-UTNM
HY[B/E]18M512160BF 512-Mbit DDR Mobile-RAM
List of Tables
List of Tables
Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Memory Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Truth Table - CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Current State Bank n - Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Current State Bank n - Command to Bank m (different bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output Slew Rate Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 AC Overshoot / Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Maximum Operating Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Self Refresh Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Full Drive Strength and Half Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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Rev.1.80, 2006-11 07092007-3E44-UTNM
HY[B/E]18M512160BF 512-Mbit DDR Mobile-RAM
List of Figures
List of Figures
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Standard Ballout 512-Mbit DDR Mobile-RAM (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 AC Overshoot and Undershoot Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Full Drive Strength and Half Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 P-VFBGA-60-1 (Plastic Very Thin Fine Ball Grid Array Package) . . . . . . . . . . . . . . . . . . . . . . . . . 20
Internet Data Sheet
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Rev.1.80, 2006-11 07092007-3E44-UTNM
HY[B/E]18M512160BF 512-Mbit DDR Mobile-RAM
Table of Contents
Table of Contents
1 1.1 1.2 1.3 1.4 2 2.1 2.1.1 2.2 3 3.1 3.2 3.3 3.4 4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definition and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Function Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pullup and Pulldown Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 4 5 6 7 7 7 8
12 12 14 17 19
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Internet Data Sheet
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Rev.1.80, 2006-11 07092007-3E44-UTNM
Internet Data Sheet
Edition 2006-11 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Under no circumstances may the Qimonda product as referred to in this Internet Data Sheet be used in 1. Any applications that are intended for military usage (including but not limited to weaponry), or 2. Any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining, sustaining or protecting human life (such applications, devices and systems collectively referred to as "Critical Systems"), if a) A failure of the Qimonda product can reasonable be expected to - directly or indirectly (i) Have a detrimental effect on such Critical Systems in terms of reliability, effectiveness or safety; or (ii) Cause the failure of such Critical Systems; or b) A failure or malfunction of such Critical Systems can reasonably be expected to - directly or indirectly (i) Endanger the health or the life of the user of such Critical Systems or any other person; or (ii) Otherwise cause material damages (including but not limited to death, bodily injury or significant damages to property, whether tangible or intangible). www.qimonda.com

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